library   ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity display is 
	port(data:in std_logic_vector(3 downto 0);
		 segment:out std_logic_vector(6 downto 0));
	end;

architecture rtl of display is
begin 
	process(data)
	begin 
		case data is 
			when "0000"=>segment<="1000000";
			when "0001"=>segment<="1111001";
			when "0010"=>segment<="0100100";
			when "0011"=>segment<="0110000";
			when "0100"=>segment<="0011001";
			when "0101"=>segment<="0010010";
			when "0110"=>segment<="0000010";
			when "0111"=>segment<="1111000";
			when "1000"=>segment<="0000000";
			when "1001"=>segment<="0010000";
			when others=>segment<="ZZZZZZZ";
		end case;
	end process;
end;
